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CY7C1020D
512K (32K x 16) Static RAM
Features
* Pin- and function-compatible with CY7C1020B * High speed -- tAA = 10 ns * Low active power -- ICC = 80 mA @ 10ns * Low CMOS Standby Power -- ISB2 = 3 mA * 2.0V Data Retention * Automatic power-down when deselected * CMOS for optimum speed/power * Independent control of upper and lower bits * Available in Pb-free 44-pin 400-Mil wide Molded SOJ and 44-pin TSOP II packages
Functional Description [1]
The CY7C1020D is a high-performance CMOS static RAM organized as 32,768 words by 16 bits. This device has an automatic power-down feature that significantly reduces power consumption when deselected.The input and output pins (IO0 through IO15) are placed in a high-impedance state when: * Deselected (CE HIGH) * Outputs are disabled (OE HIGH) * BHE and BLE are disabled (BHE, BLE HIGH) * When the write operation is active (CE LOW, and WE LOW) Write to the device by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from IO pins (IO0 through IO7), is written into the location specified on the address pins (A0 through A14). If Byte High Enable (BHE) is LOW, then data from IO pins (IO8 through IO15) is written into the location specified on the address pins (A0 through A14). Reading from the device by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appears on IO0 to IO7. If Byte High Enable (BHE) is LOW, then data from memory appears on IO8 to IO15. See the "Truth Table" on page 8 for a complete description of read and write modes.
Logic Block Diagram
DATA IN DRIVERS
A7 A6 A5 A4 A3 A2 A1 A0
ROW DECODER
32K x 16 RAM Array
SENSE AMPS
IO0-IO7 IO8-IO15
COLUMN DECODER
BHE WE CE OE BLE
A8 A9 A10 A11
A12
A13
Note 1. For guidelines on SRAM system design, please refer to the `System Design Guidelines' Cypress application note, available on the internet at www.cypress.com.
Cypress Semiconductor Corporation Document #: 38-05463 Rev. *E
*
198 Champion Court
A14
*
San Jose, CA 95134-1709 * 408-943-2600 Revised February 22, 2007
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CY7C1020D
Pin Configuration [2]
SOJ/TSOP II Top View
NC A3 A2 A1 A0 CE IO0 IO1 IO2 IO3 VCC VSS IO4 IO5 IO6 IO7 WE A4 A14 A13 A12 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE BHE BLE IO15 IO14 IO13 IO12 VSS VCC IO11 IO10 IO9 IO8 NC A8 A9 A10 A11 NC
Selection Guide
-10 (Industrial) Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 10 80 3 Unit ns mA mA
Note 2. NC pins are not connected on the die.
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CY7C1020D
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage on VCC to Relative GND [3] ... -0.5V to +6.0V DC Voltage Applied to Outputs in High Z State [3] ................................... -0.5V to VCC + 0.5V DC Input Voltage [3] ............................... -0.5V to VCC + 0.5V Current into Outputs (LOW) ........................................ 20 mA Static Discharge Voltage............................................ >2001V (per MIL-STD-883, Method 3015) Latch-Up Current..................................................... >200mA
Operating Range
Range Industrial Ambient Temperature -40C to +85C VCC 5V 0.5V Speed 10 ns
Electrical Characteristics (Over the Operating Range)
Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current Output Leakage Current VCC Operating Supply Current
[3]
Test Conditions IOH = -4.0 mA IOL = 8.0 mA
-10 (Industrial) Min 2.4 0.4 2.2 -0.5 VCC + 0.5V 0.8 +1 +1 80 72 58 37 10 3 Max
Unit V V V V A A mA mA mA mA mA mA
GND < VI < VCC GND < VI < VCC, Output Disabled VCC = Max, IOUT = 0 mA, f = fmax = 1/tRC 100 MHz 83 MHz 66 MHz 40 MHz
-1 -1
ISB1 ISB2
Automatic CE Power-Down Current--TTL Inputs Automatic CE Power-Down Current--CMOS Inputs
Max VCC, CE > VIH VIN > VIH or VIN < VIL, f = fmax Max VCC, CE > VCC - 0.3V, VIN > VCC - 0.3V, or VIN < 0.3V, f = 0
Note 3. VIL (min) = -2.0V and VIH(max) = VCC + 1V for pulse durations of less than 5 ns.
Document #: 38-05463 Rev. *E
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CY7C1020D
Capacitance [4]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Max 8 8 Unit pF pF
Thermal Resistance [4]
Parameter JA JC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Still Air, soldered on a 3 x 4.5 inch, four-layer printed circuit board SOJ 59.52 36.75 TSOP II 53.91 21.24 Unit C/W C/W
AC Test Loads and Waveforms [5]
ALL INPUT PULSES 90% 10% 90% 10%
Z = 50 OUTPUT 50 * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT 1.5V
3.0V
30 pF*
GND
Rise Time: 3 ns
(a)
High-Z characteristics: 5V OUTPUT INCLUDING JIG AND SCOPE 5 pF
(b)
Fall Time: 3 ns
R1 480
R2 255
(c)
Notes 4. Tested initially and after any design or process changes that may affect these parameters. 5. AC characteristics (except High-Z) are tested using the load conditions shown in Figure (a). High-Z characteristics are tested for all speeds using the test load shown in Figure (c).
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CY7C1020D
Switching Characteristics (Over the Operating Range) [6]
Parameter Read Cycle tpower [7] tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD
[10] [10]
Description
-10 (Industrial) Min 100 10 10 3 10 5 0 5 3 5 0 10 5 0 5 10 7 7 0 0 7 6 0 3 5 7 Max
Unit
VCC(typical) to the first access Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z CE LOW to Low Z
[9] [8, 9]
s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
OE HIGH to High Z CE HIGH to High Z
[9] [8, 9]
CE LOW to Power-Up CE HIGH to Power-Down Byte Enable to Data Valid Byte Enable to Low Z Byte Disable to High Z
[11, 12]
tDBE tLZBE tHZBE Write Cycle tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE tBW
Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low Z WE LOW to High Z
[9] [8, 9]
Byte Enable to End of Write
Notes 6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 7. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed. 8. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (c) of "AC Test Loads and Waveforms [5]" on page 4. Transition is measured when the outputs enter a high impedance state. 9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 10. This parameter is guaranteed by design and is not tested. 11. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE/BLE LOW. CE, WE and BHE/BLE must be LOW to initiate a write and the transition of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 12. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
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CY7C1020D
Data Retention Characteristics (Over the Operating Range)
Parameter VDR ICCDR tCDR [4] tR
[13]
Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time
Conditions VCC = VDR = 2.0V, CE > VCC - 0.3V, VIN > VCC - 0.3V or VIN < 0.3V
Min 2.0
Max 3
Unit V mA ns ns
0 tRC
Data Retention Waveform
DATA RETENTION MODE VCC CE 4.5V tCDR VDR > 2V 4.5V tR
Switching Waveforms
Read Cycle No.1 (Address Transition Controlled) [14, 15]
tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID
Read Cycle No.2 (OE Controlled) [15, 16]
ADDRESS tRC CE tACE OE BHE, BLE tDOE tLZOE tDBE tLZBE DATA OUT VCC SUPPLY CURRENT HIGH IMPEDANCE tLZCE tPU 50% DATA VALID tPD 50% tHZCE tHZBE tHZOE
HIGH IMPEDANCE
ICC ISB
Notes 13. Full device operation requires linear VCC ramp from VDR to VCC(min) > 50 s or stable at VCC(min) > 50 s. 14. Device is continuously selected. OE, CE, BHE and/or BLE = VIL. 15. WE is HIGH for read cycle. 16. Address valid prior to or coincident with CE transition LOW.
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CY7C1020D
Switching Waveforms(continued)
Write Cycle No. 1 (CE Controlled) [17, 18]
tWC ADDRESS
CE
tSA
tSCE
tAW tPWE WE t BW BHE, BLE tSD DATA IO tHD
tHA
Write Cycle No. 2 (BLE or BHE Controlled) [17, 18]
tWC ADDRESS
BHE, BLE
tSA
tBW
tAW tPWE WE tSCE CE tSD DATA IO tHD
tHA
Notes 17. Data IO is high impedance if OE or BHE and/or BLE= VIH. 18. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
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CY7C1020D
Switching Waveforms(continued)
Write Cycle No. 3 (WE Controlled, OE LOW) [12, 18]
tWC ADDRESS
tSCE CE tAW tSA WE tBW BHE, BLE tPWE
tHA
tHZWE DATA IO
tSD
tHD
tLZWE
Truth Table
CE H L OE X L WE X H BLE X L L H L X L L L H L L H X H X X H BHE X L H L L H L X H IO0-IO7 High Z Data Out Data Out High Z Data In Data In High Z High Z High Z IO8-IO15 High Z Data Out High Z Data Out Data In High Z Data In High Z High Z Power-Down Read - All bits Read - Lower bits only Read - Upper bits only Write - All bits Write - Lower bits only Write - Upper bits only Selected, Outputs Disabled Selected, Outputs Disabled Mode Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC)
Ordering Information
Speed (ns) 10 Ordering Code CY7C1020D-10VXI CY7C1020D-10ZSXI Package Diagram 51-85082 51-85087 Package Type 44-pin (400-Mil) Molded SOJ (Pb-free) 44-pin TSOP Type II (Pb-free) Operating Range Industrial
Please contact your local Cypress sales representative for availability of these parts.
Document #: 38-05463 Rev. *E
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CY7C1020D
Package Diagrams
Figure 1. 44-pin (400-Mil) Molded SOJ, 51-85082
51-85082-*B
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CY7C1020D
Package Diagrams(continued)
Figure 2. 44-Pin Thin Small Outline Package Type II, 51-85087
51-85087-*A
All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05463 Rev. *E
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(c) Cypress Semiconductor Corporation, 2006-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY7C1020D
Document History Page
Document Title: CY7C1020D, 512K (32K x 16) Static RAM Document #: 38-05463 REV. ** *A *B ECN NO. 201560 233695 263769 Issue Date See ECN See ECN See ECN Orig. of Change SWI RKF RKF Description of Change Advance Data sheet for C9 IPP 1) DC parameters modified as per EROS (Spec # 01-0216) 2) Pb-free Offering in the `Ordering Information' 1) Corrected pin #18 on SOJ/TSOPII Pinout (Page #1) from A15 to A4 2) Changed IO1 - IO16 to IO0 - IO15 on the Pin-out diagram 3) Added Tpower Spec in Switching Characteristics Table 4) Added Data Retention Characteristics Table and Waveforms 5) Shaded `Ordering Information' Reduced Speed bins to -10, -12 and -15 ns Converted from Preliminary to Final Removed Commercial Operating range Removed 12 ns speed bin Added ICC values for the frequencies 83MHz, 66MHz and 40MHz Updated Thermal Resistance table Updated Ordering Information Table Changed Overshoot spec from VCC+2V to VCC+1V in footnote #3 Changed ICC specs from 60 mA to 80 mA for 100MHz, 55 mA to 72 mA for 83MHz, 45 mA to 58 mA for 66MHz, 30 mA to 37 mA for 40MHz
*C *D
307594 560995
See ECN See ECN
RKF VKN
*E
802877
See ECN
VKN
Document #: 38-05463 Rev. *E
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